The performance, reliability and package density of many types of compound semiconductor devices, including integrated circuits (ICs), are constrained by the devices' ability to dissipate heat. For example, most members of the group II-IV and III-V type of compound semiconductor have poor thermal conductivity. Therefore, in order to improve one of these devices' high power operating characteristics, one must increase the device's heat dissipation capability by reducing the heat conduction pathlength between the device's heat generating regions and an external heat sink. At the same time, reducing the heat conduction path length must not significantly degrade the device's performance or reducing the mechanical strength of the wafer substrate during the manufacturing process. The best known group III-V compound semiconductor is gallium arsenide (GaAs), which is used to make many kinds of GaAs devices, including some with high power GaAs field effect transistors (FETs) and the high power GaAs/AlGaAs heterojunction bipolar transistors (HBTs). The main sources of heat generation in these devices are: (a) the drain-source channels of the GaAs FETs, (b) emitter finger regions of the GaAs/AlGaAs HBTs, and (c) resistors on the GaAs ICs.
In U.S. Pat. No. 4,189,682 and U.S. Pat. No. 4,189,688, Sechi describes providing heat dissipation by mounting a heat sink to the top of the device. This technology is generally known as the flip mounting technology, since the device is first turned upside down before mounting on metal heat sink posts. This technology requires extra components, extra manufacturing equipment and skilled operators in a time consuming aligning/mounting task. The heat dissipation is still not very efficient, since the heat sink is typically placed at some distance away from the heat sources and through poor thermal conductivity paths. Therefore, this technology is not very much in common use.
Another class of prior art is to place one of the electrodes (either the gate or the source) on the backside of the wafer connecting to a heat sink. The heat dissipation capability of this configuration is generally very high. For example, in U.S. Pat. No. 4,092,660, Blocker describes placing the gate on the backside of the wafer and connecting it to a heat sink for efficient heat dissipation. However, the large gate to source capacitance resulting from this configuration would seriously degrade its high frequency performance (for example, above 4 GHz). Another problem with this configuration, which severely limits its application to ICs, is the requirement that the heat sink on the back surface of the substrate be physically connected to one of the electrodes of the device formed on the front surface of the substrate.
Another configuration has recently been described by workers from two leading manufacturers of GaAs devices: U.S. Pat. No. 4,807,022, Kazior et al. from Raytheon Company and U.S. Pat. No. 4,842,699, Hua et al. from Avantek, Inc. In this configuration, via holes are etched from the back of the wafer substrate all the way through the wafer substrate to reach the metal pads of the electrodes of the device on the front side of the wafer substrate, and then high thermal conductivity materials are deposited in these via holes to improve the heat dissipation of the device. This configuration is not very efficient in heat dissipation because the via holes have limited cross-sectional area and are generally located some distance away from the heat generating regions of the device. An improved configuration of this class, known as the opposed gate-source transistor (OGST) was recently reported by a group from Cornell University, where the source is placed on the backside of the wafer connecting to a heat sink. (See article entitled: "The opposed gate-source transistor", which is published in March 1987 issue of Microwaves & RF, pages 155 through 165, and authored by K. Rauschenbach and C. A. Lee). This structure uses an AlGaAs etch stop layer for controlled etching of wells on the backside of the wafer. However, this particular structure is not compatible with any undoped buffer layer above the etch stop layer and thus it is not applicable to any GaAs planar FETs. This structure also suffers from the same limitation as the Blocker type of device described above, since its heat sink on the back surface of the substrate is physically connected, through a hole in the etch stop layer, to one of the electrodes of the device formed on the front surface of the substrate. In addition, this structure requires that the drain and the source be placed at a small distance apart (a few tenths of a .mu.m), which results in low breakdown voltage between the drain and the source. Furthermore, the large drain to source capacitance of this structure, since the drain is separated from the source by merely a few tenths of a .mu.m, should result in poor high frequency performance.
A recent paper proposes yet another method to improve the heat dissipation in high power GaAs HBTs by simply fabricating the GaAs device on silicon (Si) wafer substrate, which has higher thermal conductivity and 3 times higher power handling capability than GaAs substrate. This paper is entitled: "Thermal design studies of high-power heterojunction bipolar transistors", which is published in May 1989 issue of IEEE Transactions on Electron Devices, Vol. 36, pages 854-863, and authored by G.-B. Gao et al. However, the technology of growing GaAs on Si is still in the early developmental stage with many unsolved manufacturing problems.
The most widely practiced prior art in high power GaAs FETs and GaAs ICs nowadays is simply to manufacture devices on GaAs wafer substrate and then reduce the heat conduction pathlength by thinning the thickness of the whole wafer substrate to about 100 .mu.m. The active device of this class is first fabricated on the frontside of a starting GaAs wafer substrate, typically 250-500 .mu.m thick, then the backside of the wafer is thinned by mechanical or chemical means until the thickness of the wafer is about 100 .mu.m, and finally a high thermal conductivity metal layer, typically either gold (Au) alone or a combination of palladium (Pd) and gold, is electro-chemically plated or thermally evaporated onto the backside of the wafer before the backside of the wafer substrate is soldered or epoxied to a heat sink carrier. Obviously, the thinner the GaAs wafer is, the better the heat dissipation will be for the device. However, the wafer substrate thickness of 100 .mu.m is considered to be a practical compromise, because at this thickness the wafer substrate still possess both sufficient mechanical strength to withstand subsequent process handling and sufficient dielectric separation for transmission lines formed between GaAs IC's strip conductors on the frontside of the wafer substrate and the ground plane on the backside of the wafer substrate.
A further improvement of the above described prior art is to further reduce the heat conduction pathlength by selectively thinning the wafer substrate underneath the heat generating regions of the device to form etch wells (or "tub structures") and then back fill these etch wells with materials of high thermal conductivity, such as Au and Pd. This method, however, suffers from the high risk of etch-through if the distance between the bottom of the etch well and the active device is reduced to a value close to the total thickness variation of the final wafer, which is the sum of the thickness non-uniformity of the starting wafer and additional thickness variations created during the wafer thinning process. Therefore, this total thickness variation of the final wafer, which usually can be as much as 10-20 .mu.m, places a practical limitation on the reduction of the heat conduction pathlength through selectively thinning of the wafer in the form of etch wells (or "tub structures"). This practical limitation imposed by the thickness variation of the final wafer is illustrated by the following three examples.
Example one: Plessey PLC of United Kingdom recently announced (see Electronics, Feb. 4, 1988, p. 51) the development of a high power GaAs FET process, by which wells are etched in the backside of a 200 .mu.m thick GaAs wafer beneath the high power GaAs transistors. Then Au is filled in the wells as the high thermal conductivity material. This process reduces the heat conduction pathlength to about 50 .mu.m by placing the Au to about 50 .mu.m from the FET power transistor. Example two: a similar technique to form uniformly etched wells (or "tub structures") in the backside of a 100 .mu.m thick GaAs IC beneath the heat generating regions is described in detail by Tong et al from Raytheon Company, a major manufacturer of GaAs devices and ICs, in a recent patent (U.S. Pat. No. 4,794,093; issued on Dec. 27, 1988). In this patent, Tong et al reported a method to reduce the heat conduction pathlength to about 20 to 50 .mu.m (or 20 to 50% of the thickness of the 100 .mu.m thick wafer substrate). Example three: the largest GaAs power FETs in commercial use today, Fujitsu Model FLM 4450-8B, which has 36 dBm output power per chip and 8 dB gain at 4 to 5 GHz. The total gate width is 12 millimeters with gate to gate spacing of 20 .mu.m and with 84 gate fingers. The semi-insulation GaAs wafer substrate is thinned to about 40 .mu.m and then a 35 .mu.m thick Au is plated on the backside.
The above mentioned heat conduction pathlengths, which are the distances between the high thermal conductivity material and the heat generating regions, are respectively 50 .mu.m for the Plessey FETs, 20 to 50 .mu.m for the devices described in the Raytheon patent, and 40 .mu.m for the Fujitsu FETs. These are the smallest heat conduction pathlengths currently known for GaAs devices and ICs.
As is shown later that this invention is able to provide a practical structure consisting of a combination of an epitaxial undoped GaAs buffer layer and an epitaxial AlGaAs etch stop layer to overcome etch-through and other problems and to achieve a much reduced heat conduction pathlength of about 0.2 to 10 .mu.m. This improved heat dissipation structure with a much reduced heat conduction pathlength would result in a significant improvement of device life and performance.
It should be noted that an undoped AlGaAs buffer layer as an optical window has been used in Burris type of optical detection devices. A representative Burris device is described in U.S. Pat. No. 4,416,053, by Figueroa et al. which shows the use of an undoped Al.sub.x Ga.sub.1-x As buffer layer as an optical window. The x value required for these devices is usually higher than 0.35, which would make the buffer layer to contain much too many traps and DX centers to be useful as a buffer layer for stable high power high frequency GaAs devices and ICs.
It is an object of the present invention to provide a high power compound semiconductor device or IC, essentially those of the group III-V compound semiconductor type, with a practical and improved heat dissipation structure by selectively placing materials of high thermal conductivity in etch wells located underneath and within 0.2 to 10 .mu.m from the heat generating regions of the active device, while minimizing the drain-to-source parasitic capacitance, and at the same time improving the mechanical strength (or to reduce the fragility) of the device.